Elementary cellular automata realized by stateful three-memristor logic operations

Cellular automata (CA) are computational systems that exhibit complex global behavior arising from simple local rules, making them a fascinating candidate for various research areas. However, challenges such as limited flexibility and efficiency on conventional hardware platforms still exist. In this study, we propose a memristor-based circuit for implementing elementary cellular automata (ECA) by extending the stateful three-memristor logic operations derived from material implication (IMP) logic gates. By leveraging the inherent physical properties of memristors, this approach offers simplicity, minimal operational steps, and high flexibility in implementing ECA rules by adjusting the circuit parameters. The mathematical principles governing circuit parameters are analyzed, and the evolution of multiple ECA rules is successfully demonstrated, showcasing the robustness in handling the stochastic nature of memristors. This approach provides a hardware solution for ECA implementation and opens up new research opportunities in the hardware implementation of CA.


Methods
Elementary cellular automata (ECA) are one-dimensional cellular automata characterized by cells that can exist in two states: "0" or "1".In ECA, the state of a cell in the next generation is determined by the current states of both the cell and the cell's two adjacent cells.There are 2 3 = 8 possible patterns for a cell and its two neighbors ( P 0 = 000 , P 1 = 001 , ..., P 6 = 110 , P 7 = 111 ).The dimension of ECA is wrapped around, hence the left neighbor of the leftmost cell is the rightmost cell, and the right neighbor or the rightmost cell is the leftmost cell.Figure 1a shows the evolutionary process of ECA governed by rule 110.This rule serves as the evolution principle, dictating the state transitions of each cell in the subsequent generation.The rule number is interpreted as a binary representation, such as 110 (in decimal), which translates to 01101110 in binary.Each digit determines the state of the cell in the next generation.For instance, the i th digit (counting from right to left) determines the state of the i th cell (counting from right to left) in the next generation.There are 2 23 = 256 possible rules of ECA (from 0 to 255).
Figure 1b illustrates the hard-switching characteristics of the memristor model employed in this work, which is adapted from the mean metastable switch (MMSS) memristor model proposed by Knowm Inc 23 and closely resemble the switching behaviors of a memristor like the Au/HfO 2 /Ni memristor reported in our previous study 24 .
Further details about the model are described in Supplementary Note 1.In logic operations based on memristors, the low-resistance state (LRS) is defined as logical "1", while the high-resistance state (HRS) is defined as logical "0".To align with the characteristics of the memristor, the evolution of the ECA can be categorized into two groups of logic operations: SET and RESET, as depicted in Fig. 1c.The SET operation corresponds to the initial state of "0", while the RESET operation corresponds to the initial state of "1".
Figure 2a shows the circuit schematic of the memristor-based ECA.Each cell consists of two parallel memristors connected in parallel with its neighboring cells, with one being the main memristor and the other being the dummy memristor.All cells are interconnected at their lower potential node, and a load resistor R load is connected from this node to ground.The resistance of R load is chosen to be equal to the LRS of the memristor.For clarity and easy reference, we have designated three specific cells as A, B and C. Each cell consists of two parallel memristors.The parallel memristors of the three cells are labeled as A and A ′ , B and B ′ , and C and C ′ , respectively.The memristor A, B and C are defined as the main memristors, while the memristor A ′ , B ′ and C ′ are defined as the dummy memristors in each cell.The voltages applied to the top-electrode of each memristor are defined as V A , V A ′ , V B , V B ′ , V C , and V C ′ , respectively.The voltages applied to R load is denoted as V load .The node voltage of the common line connected to the bottom-electrode of each memristor is defined as V ref .
In the circuit, all switches (i.e., the MOSFETs shown in Fig. B is the current cell, its neighbors are cell A (on the left) and C (on the right).When voltage V B is applied, the potential difference across the memristor B should be The main memristors and dummy memristors store the state of the cell for different purposes.The new state of cell B for the next generation is determined by the relationships among the parameters R A ′ , R B , R C ′ , R load , V A ′ , V B , V C ′ , and V load , respectively.By appropriately adjusting the voltages, the specified logic operation can be realized.To ensure the completeness of the ECA algorithm, two logic operation strategies were introduced: the "non-floating R load " strategy and the "floating R load " strategy, as shown in Fig. 2b,c, respectively.The rules corresponding to the "non-floating" strategy and "floating" strategy are detailed in Supplementary Note 2. The circuit underwent thorough analysis to derive the mathematical principles governing the interactions between the parameters.
Firstly, the "non-floating R load " strategy is analyzed.When the state of cell B is "0", the SET operation is per- formed.During this process, the relationships among the parameters and V load are obtained using Kirchhoff 's Circuit Laws, as shown in Eq. ( 1).
The value of R load is much smaller than R HRS , which can be considered negligible in the above equation when ABC ∼ (000) (i.e., the cell state of cell A, B and C is "0", "0" and "0", respectively).Similarly, the value of R LRS R load is much smaller than R LRS R HRS and R load R HRS , which can be neglected in the equation when ABC ∼ (001), (100) or (101) .Therefore, Eq. ( 1) can be simplified as Eq. ( 2).

The values of V
SET is greater than the SET threshold of memristor, the state of cell B changes from "0" to "1".Otherwise, the state of cell B remains "0".By applying appropriate V A ′ , V B , V C ′ and V load , the conditional SET operation with the "non-floating R load " strategy can be realized. (1) . (2) . To ensure the completeness of the ECA rules from 0 to 255, it is necessary to employ the "floating R load " strat- egy during the SET stage.The relationships among the parameters R A ′ , R B , R C ′ , V A ′ , V B and V C ′ can be obtained from the Kirchhoff Circuit Laws, as shown in Eq. (3).
As the value of R LRS is much smaller than R HRS , which can be considered negligible in the above equation when ABC ∼ (001), (100) or (101) .Therefore, Eq. ( 3) can be simplified as Eq. ( 4), The values of V (000) SET and V (101) SET is greater than the SET threshold of the memristor, the state of cell B changes from "0" to "1".Otherwise, the state of cell B remains "0".By applying appropriate V A ′ , V B and V C ′ , conditional SET operation with the "floating R load " strategy can be realized.
When the state of cell B is "1", the RESET operation is performed.For this operation, the relationships among the parameters and V load are obtained from Kirchhoff 's Circuit Laws, as shown in Eq. ( 5).
The value of R LRS R load is much smaller than R LRS R HRS and R load R HRS , which can be considered negligible in the above equation when ABC ∼ (010), (011) or (110) .Therefore, Eq. ( 5) can be further simplified as Eq. (6).
The value of V RESET and V (111) RESET is greater than RESET threshold of memristor, state of cell B changes from "1" to "0".Otherwise, the state of cell B remains "1".By applying appropriate V A ′ , V B , V C ′ and V load , the conditional RESET operation can be realized.Being dif- ferent from the SET stage, the RESET stage of all ECA rules can be realized based on the "non-floating R load " strategy.Therefore, the "floating R load " strategy is not necessary for the RESET stage.
There are 16 types of conditional SET stages and 16 types of conditional RESET stages for the ECA rule, ranging from 0 to 255.Most of them can be accomplished through a single operation, except for SET operations with P 5 P 4 P 1 P 0 = (0110) and (1001) and RESET operations with P 7 P 6 P 3 P 2 = (0110) and (1001) .These specific SET/RESET stages can be achieved by performing two consecutive steps of operations.

Results and discussion
Figure 3 demonstrates the stateful three-memristor logic operations for ECA through simulation.Circuit-level simulation is conducted using LTspice XVII, with a Python-LTspice interface developed to control the entire ECA evolution process, providing flexibility to modify rules and collecting circuit parameters.The HRS and LRS of the memristors and the load resistor were set as follows: R HRS = 5 × 10 6 , R LRS = 5 × 10 2 and R load = 5 × 10 2 ; where the positive/negative threshold of memristor was defined as: V SET = 3V , V RESET = −3V , respectively.The node potentials during the SET stage and RESET stage for Rule 171 and Rule 116 of the memristor-based ECA are shown in Fig. 3a,b, respectively.Rule 171 employs the "non-floating" strategy; while Rule 116 employs the "floating" strategy.Figure 3c,d show the electrical characteristic of the memristor A, B and C during evolution, respectively.The red, blue and green line corresponds to the memristor A ′ , B and C ′ , respectively.Firstly, the READ operation was implemented, a voltage pulse with amplitude 0.1V and width 12 μs was sequentially applied , ABC ∼ (000) , ABC ∼ (101) . (5) . Vol.:(0123456789) Scientific Reports | (2024) 14:2677 | https://doi.org/10.1038/s41598-024-53125-w to memristor A ′ , B and C ′ , for reading the current state of memristor (cell).The resistance state of memristor can be measured by the magnitude of the reading current, where the HRS ( < 10 µA ) and the LRS ( ≥ 10 µA ).Subsequently, the conditional SET/RESET operation was carried out, the pulses with amplitude V A ′ , V B and V C ′ and width 12 μs were simultaneously applied to memristor A ′ , B and C ′ , respectively.After that, another READ operation was implemented to read the state of each memristor.The results of the stateful three-memristor logic operations for Rule 171 and Rule 116 are consistent with the predicted outcomes.The ECA typically involves multiple cycles for evolution, requiring a comprehensive hardware control approach.Figure 4 illustrates the flowchart of the memristor-based ECA evolution.In this circuit, the initial state of all memristors is set to "0".Therefore, the memristors in state "1" are initially RESET to the HRS.Subsequently, each cell state of the ECA is mapped to the corresponding memristors.For the cells in state "1", the  corresponding memristors are SET to the low-resistance state (LRS).Following this, a small fixed voltage pulse is applied to measure the current flowing through each memristor.The resistance state (HRS or LRS) of the memristor can be determined based on the measured current, which is then used to determine whether each cell should undergo the SET stage or RESET stage during evolution.After completing the SET stage for all cells in state "0" and the RESET stage for all cells in state "1", dummy memristors are employed to synchronize the cell states for the next generation.The COPY operation 21 is utilized to synchronize the states of the main memristors with their corresponding dummy memristors.Once this step is completed, another evolution cycle is implemented to continue the ECA evolution process.
Figure 5 shows the evolution of the memristor-based ECA using different rules: 30, 54, 94, 110, 118 and 190.The ECA comprises 32 memristors, i.e., 16 main memristors and 16 dummy memristors, forming a total of 16 cells.The ECA's initial state is specified as "1" in the 8th cell from the left, while the remaining cells are set to "0".It undergoes evolution for a total of 15 cycles.The results of the evolution align with the expected outcomes for all rules, demonstrating the accuracy of the proposed memristor-based ECA.The system exhibits solid robustness even in the presence of stochastic characteristics, as evidenced by the successful evolution despite the inclusion of 10% white noise in R ON and R OFF and a 5% white noise component in the V ON and V OFF in the adapted MMSS memristor model.Additionally, the error tolerance of parameters R ON , R OFF , V ON , and V OFF in the adapted MMSS memristor model is analyzed in Supplementary Note 3. The results of the evolution are consistent with the expected outcomes for all rules, demonstrating the accuracy and robustness of the proposed memristorbased ECA.Despite some fluctuations in the resistance of the memristors during the evolution process, they do not have an impact on the overall results.

Conclusion
In this study, we have introduced a memristor-based ECA circuit design capable of encompassing ECA rules from 0 to 255.Memristors serve as both storage elements for cell states and computing elements of ECA evolution by applying appropriate voltages to each node.The ECA evolution process is efficiently divided into two stages, SET and RESET, by leveraging the characteristics of memristors and employing stateful three-memristor logic operations.Through detailed circuitry analysis, we have successfully identified the mathematical principles that govern each parameter of the proposed memristor-based ECA.This comprehensive understanding enables us to effectively achieve the desired ECA rule.SPICE simulations were conducted to demonstrate the evolution process of the memristor-based ECA for various rules.The proposed approach successfully achieved the expected evolution patterns of the memristor-based ECA and exhibited solid robustness in handling the inherent stochasticity of memristors.With its simplicity, minimal operational steps and high flexibility, the proposed approach opens an avenues for further research in the hardware implementation of CA.

Figure 1 .
Figure 1.(a) Elementary cellular Automata, (b) typical hard switching characteristics of the memristor, and (c) logic operations divided into two stages: SET and RESET.

Figure 3 .
Figure 3. Node potentials during the evolution of memristor-based ECA with (a) Rule 171 and (b) Rule 116; The elertrical charactristic of memristor during evolution with (c) Rule 171 and (d) Rule 116.